About This Course
A unique collection of questions which I was asked in my interviews. I found that these questions were a common factor in many interviews that even my colleagues asked in the interviews.
The fundamental questions based on the TRIFECTA of Circuit Analysis (more about this in my course) were more or less mandatory in all the interviews at all levels of hiring.
A special mention on how to attend a telephonic interview on Analog Design.
Learning Objectives
Specific knowledge on the methods and contents of (almost) all interviews on Analog Circuit Design.
Requirements
- 1. A thorough understanding on the fundamentals of circuit analysis
- 2. Learn about the intuitive nature of circuits
- 3. Solve a lot of questions before going to an interview.
Target Audience
- All interview aspirants
Curriculum
8 Lessons50m
Unique Interview Questions
MOST IMPORTANT – TRIFECTA of Circuit Analysis7:34
Lessons to learn from Ideal Opamp5:10
Finite Open Loop Gain8:10
Current Flowing in a diode11:29
Fun Facts of Diodes4:10
Importance of Voltage Regulation and Negative Feedback8:54
Preparing for a Telephonic Interview – Analog Design Engineer3:50
Summary1:12
Test your knowledge with GATE ECE Questions
Your Instructors
Dr Javed GS
Tech Lead / Analog Manager
A creative problem solver for innovative solutions and passionate analog design manager.
Analog Lead for Parallel Memory Interface/ Die-to-Die Interconnnect
IEEE Eta Kappa Nu HKN Inductee - Class of 2016 - Mu Xi Chapter
Expertise:
Analog IC Design,
High Speed SerDes Transceivers (1.25 - 20 Gbps),
High Speed Low Power Interfaces (PCIe G4, MIPI MPHY G4, USB 3.2, Ethernet 10GE) - Datapath and Clockpath
PLL (2.5GHz Ring, 5 GHz Ring and 10GHz LC),
Sigma Delta ADC for Lab on Chip (13.5b @ 10KHz)
Frequency Doublers for 20GHz
As an engineer with 12+ years of working experience in Analog IC design, I am fortunate to have solved customers design problems. At Terminus Circuits (3.4 years), I have contributed on design and development of High Speed Interface IP like USB3.2/PCIeG4/MIPI MPHY G4/Multi Protocol SerDes, each with its own TEST CHIP (SoC) and manage a cross functional team of 15 Analog Designers. This has resulted in 4 Journals and 5 IEEE Conferences publications.
#Project40GbpsSerDes
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Material Includes
- 7-Day Money-Back Guarantee
- Lifetime access
- Access on mobile and TV
- Q&A Section with instructor
- Certificate on completion
