A creative problem solver for innovative solutions and passionate analog design manager. Analog Lead for Parallel Memory Interface/ Die-to-Die Interconnnect IEEE Eta Kappa Nu HKN Inductee - Class of 2016 - Mu Xi Chapter Expertise: Analog IC Design, High Speed SerDes Transceivers (1.25 - 20 Gbps), High Speed Low Power Interfaces (PCIe G4, MIPI MPHY G4, USB 3.2, Ethernet 10GE) - Datapath and Clockpath PLL (2.5GHz Ring, 5 GHz Ring and 10GHz LC), Sigma Delta ADC for Lab on Chip (13.5b @ 10KHz) Frequency Doublers for 20GHz As an engineer with 12+ years of working experience in Analog IC design, I am fortunate to have solved customers design problems. At Terminus Circuits (3.4 years), I have contributed on design and development of High Speed Interface IP like USB3.2/PCIeG4/MIPI MPHY G4/Multi Protocol SerDes, each with its own TEST CHIP (SoC) and manage a cross functional team of 15 Analog Designers. This has resulted in 4 Journals and 5 IEEE Conferences publications. #Project40GbpsSerDes