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Semiconductor Industry Daily News & Updates

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Semiconductor Industry Daily News & Updates

  • In the business press today I still find a preference for reporting proof-of-concept accomplishments for AI applications: passing a bar exam with a top grade, finding cancerous tissue in X-rays more accurately than junior radiologists, and so on. Back in the day we knew that a proof-of-concept, however appealing, had to be followed… Read More […]
  • David Zhi LuoZhang is Co-Founder and CEO of Bronco AI with extensive experience in building AI systems for mission-critical high-stakes applications. Previously while at Shield AI, he helped train AI pilots that could beat top human F-15 and F-16 fighter pilots in aerial combat. There, he created techniques to improve ML interpretability… Read More The […]
  • For markets such as data center, high-performance computing, networking and AI accelerators the battle cry is often “copper is dead”. The tremendous demands for performance and power efficiency often lead to this conclusion. As is the case with many technology topics, things are not always the way they seem. It turns out a lot … […]
  • By Nir Sever, Senior Director Business Development, proteanTechs Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring Effective thermal management is crucial to prevent overheating and optimize performance in modern SoCs. Inadequate temperature control due to inaccurate thermal sensing… Read More The post Thermal Sensing Headache Finally Over for 2nm […]
  • In a rapidly evolving semiconductor landscape, where AI demands unprecedented computational power and efficiency, Synopsys has deepened its partnership with TSMC to pioneer advancements in AI-driven designs and multi-die systems. Announced during the TSMC OIP Ecosystem Summit last week, this collaboration leverages … Read More The post Synopsys and TSMC Unite to Power the Future […]
  • A new technical paper titled “Scaling High-Performance Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides” was published by researchers at Stanford University, HORIBA Scientific, and SLAC National Accelerator Laboratory. Abstract “Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely… […]
  • A new technical paper titled “Coherent diffractive imaging simulations for wafer inspection of periodic structures” was published by researchers at the Paul Scherrer Institute and Samsung. Excerpt “We present a study of phase retrieval algorithms applied to the metrology of copper pad topography for hybrid bonding. We demonstrate that by including a priori information in the update… […]
  • A new technical paper titled “Leveraging Modularity of Chiplets to Form a 4×4 Automotive FMCW-Radar in an eWLB-Package” was published by researchers at Ruhr University Bochum, Fraunhofer Institute, University Bremen, Infineon and WavesenseDD GmbH. Abstract “Dividing a System on Chip (SoC) into multiple smaller chiplets and embedding them into a single package has gained significant… […]
  • A new technical paper titled “Towards efficient wafer visual inspection: Exploring novel lightweight approaches for anomaly detection and defect segmentation” was published by researchers at Fraunhofer Portugal AICOS. Excerpt “AI has made significant strides in unsupervised anomaly detection and supervised defect segmentation, yet its application to wafer inspection remains underexplored. This work bridges these fields… […]
  • OpenAI DRAM capacity deals in Korea; $4.4B IC equipment merger; Taiwan rebuffs US' 50-50 split offer; EU Chips Act revision; Meta buys RISC-V startup; foundry report; imec transition; NIST disses DeepSeek; China's litho overblown; H-1B weighted system. The post Chip Industry Week in Review appeared first on Semiconductor Engineering.
  • A new technical paper titled “AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems” was published by researchers at University of Central Florida and Louisiana State University. Abstract “The rapid adoption of chiplet-based heterogeneous integration is reshaping semiconductor design by enabling modular, scalable, and faster time-to-market solutions for AI and high-performance computing. However,… […]
  • A new technical paper titled “VMSCAPE: Exposing and Exploiting Incomplete Branch Predictor Isolation in Cloud Environments” was published by researchers at ETH Zurich. Abstract “Virtualization is a cornerstone of modern cloud infrastructures, providing the required isolation to customers. This isolation, however, is threatened by speculative execution attacks which the CPU vendors attempt to mitigate by… […]
  • A new technical paper titled “Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage” was published by researchers at Nanyang Technological University, Cornell University, Altera, University of Waterloo and University of Toronto. Abstract “Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices. For instance,… […]
  • From predictive maintenance to excursion monitoring, AI is redefining yield management in multi-die assembly. The post Smarter Packaging: How AI is Reshaping Assembly and Materials Control appeared first on Semiconductor Engineering.
  • Local layout effect; power plane capacitance; HBM4; more double-precision division; SDV framework. The post Blog Review: Oct. 1 appeared first on Semiconductor Engineering.