Also known as Electronic System Level Synthesis and C Synthesis, High-Level Synthesis is an automated design procedure, that converts the algorithmic description of a system into the corresponding hardware circuit. In this process, which is actually a part of the high-level design flow, the system behaviour is described at a very high level of abstraction. This method improves productivity and reduces the chance of error.

Brief History

Synopsys introduced Behavioral Compiler, the first generation behavioural synthesis tool, in 1994. Verilog was used as the input language. 10 years later, various next-generation High-Level Synthesis(HLS) tools were introduced in the market. These tools offered circuit synthesis, described in a high-level language and Register Transfer Level. Manufacturers of these tools provided extensive PC support for a wide range of tool issues.

How It Is Done?

The first step in HLS is to implement the system algorithm in a high-level language, such as ANSI C, C++, System C, etc. After that, the synthesis tool generates the technical details, which is required for hardware implementation. Most of the HLS design methods use conventional logic synthesis tools by generating a Register Level Transfer (RTL) logic implementation from the system algorithm. The RTL logic is used by the traditional logic synthesis tools to generate a gate-level design. The HLS tools convert the partially timed functional code into a fully timed RTL design. The basic objective of HLS is to enable the designers to develop and test the hardware efficiently. It also gives the designers better control over the design architecture optimization.

Abstraction Levels

Hardware design could be developed at multiple levels of abstraction. The most common abstraction levels are Algorithmic Level, Register Transfer Level and Gate Level.

Logic Synthesis And HLS Comparison

Logic Synthesis employs Register Level Transfer design, while the High-Level Synthesis uses a higher level of abstraction, in which the algorithmic functions are written in high-level languages, like ANSI C, C++ or System C. The hardware designer constructs the interconnect protocol and the module functionality. The HLS tools translate the functional code into Register Transfer Level design by generating the cycle by cycle details of hardware implementation.

Source Inputs For HLS

The most commonly used source inputs to the High-Level Synthesis are based on high-level languages, such as ANSI C, C++, System C, etc. Bit accurate executable specification is also used as inputs. To decide the proper input format for a particular application needs proper expertise which could be provided by an experienced network support provider.

Process Stages

The HLS process consists of several stages. Numerous tools implement these stages in different sequence using different algorithms. The most common process stages are Algorithm Optimization, Lexical Processing, Control and Data flow analysis, Resource Allocation, Library Processing, Scheduling, Output Processing, Register Binding, Functional Unit Binding, Input Processing, etc. These different process stages should be implemented under the guidance of a computer support provider.

Architectural Restrictions

Building hardware architecture and writing Verilog or VHDL code needs considerable expertise and effort. The code writing process in a high-level language should follow not only the synthesis standard but also meet the timing requirements. The function and interface specification should be implemented correctly. The most common constraints are memory, interface, hierarchy, loop, timing, iteration, etc. Issues related to these restrictions should be resolved with the help of network support providers.

PC Support For HLS

Various vendors, such as Cadence Design Systems, Bluespec, Synopsys, ChipVision provide extensive network support for High-Level Synthesis problems. Apart from these manufacturers, many third-party vendors also offer high-quality computer support for different HLS issues.