1. Detail synthesis flow, What are the inputs required and hand-off
2. Detail Physical Design Flow? What are the inputs required and hand-off
3. What is OCV, AOCV differences?
4. With respect to Freq vs setup and freq vs hold ?
5. What is Clock gating ?
6. What is local skew Global skew?
7. What are DRC and logical DRC?
8. What does lib, sdc, lef, spef contains, what all parameter it contains?
9. What is MCMM? for hold analysis which corner analysis should be done.
10. Typically in a design, how many corners are used in a design, how do we decide?
11. What is cross talk? How to avoid crosstalk? All 4 case of Agg* and VICT*
12. What are the optimization techniques used for timing?
13. What are the Physical values set in SDC. What is set_input_delay and set_output_delay.
14. What is Temperature Inversion?
15. What is uncertainty and give the equations of setup and hold. Develop the clock waveform in both the cases.
16. What are gates and instance and to get them in synthesis?
17. What is Clock domain and clock domain crossing?
18. Difference between compile, simulation and synthesis
19. Synthesis to generic, to mapped and placed
20. Clock uncertainty, clock skew, clock latency, clock jitter
21. Why is the term lockup latch is used explain it by developing a scenario.
22. Explain the half cycle path with proper diagrams.
23. What are the different timing derates you have used in your project explain them with a
24. How do you fix the Max Transition? Why is it the necessity to specify the output load and Input
25. How do you find the find out the instances in a netlist and its count with command.
26. What is the flow followed in your previous project & the challenges faced in your project?
27. Everything in detail what we have in the skeleton script (Synthesis flow) commands
28. In SDC file (set clock_uncertainity, set clock_latency, set max_transition, set max_capacitance,  set max_fanout, set_input_delay, set_output_delay, set_drive, set_load) use of each command  in detail?
29. Low power techniques and ways to reduce leakage power in synthesis
30. Different types of optimization techniques.(Area,power,timing & performance)
31. SI analysis setup ( crosstalk noise and crosstalk delay, ways to fix SI)
32. Difference between block level and chip level design
33. Different types of wireload models. Where are the used?
34. What are different PVT Conditions. How it effects on delay? (dig. W.r.t delay P,V,T)
35. What is short circuit power? Explain short circuit power by drawing CMOS inverter
36. Why we choose different corners for timing closure?
37. Calculate max frequency for two flops connected back to back with no combo delay. Clk to Q of first flop is 200ps and Setup of second flop is 200ps.
38. Need of CTS? Why we fix hold only after CTS?
39. Find the max frequency between the two flops. cq = 0; Tsu = 100ps; Th = 100ps;Tcombo = 100ps;
40. Why can’t we use normal buffer in clock tree synthesis?

Recommended Books

Explore the discussion on Synthesis Interview questions at Semiconductor Club Community Forum.