About This Course
In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
DISCLAIMER:
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Learning Objectives
By enrolling to this course one will get the understanding of basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Requirements
- The Free Courses does not include Certificate and Q&A Sections.
Target Audience
- Electronics Engineers Students and Professionals.
Curriculum
12 Lessons13h 12m 18s
Introduction
This topic covers the motivation for the course and an introduction to the chip design process.
Introduction46:28
Verilog
Logic Synthesis
Timing (STA)
Moving to the Physical Domain
Standard Cell Placement
Clock Tree Synthesis
Routing
Packaging and I/O Circuits
Sign Off and Chip Finishing
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Material Includes
- Video Lessons
