Digital VLSI Design – RTL to GDS

semiconductor
SC Instructor
Last Update September 1, 2021
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About This Course

In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).

DISCLAIMER:

These videos are publicly available on the internet for free hence they may contain some advertisements. The ads earning goes to the respective instructor.

Learning Objectives

By enrolling to this course one will get the understanding of basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).

Requirements

  • The Free Courses does not include Certificate and Q&A Sections.

Target Audience

  • Electronics Engineers Students and Professionals.

Curriculum

12 Lessons13h 12m 18s

Introduction

This topic covers the motivation for the course and an introduction to the chip design process.
Introduction46:27

Verilog

Logic Synthesis

Timing (STA)

Moving to the Physical Domain

Standard Cell Placement

Clock Tree Synthesis

Routing

Packaging and I/O Circuits

Sign Off and Chip Finishing

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Free
Level
All Levels
Duration 13.2 hours
Lectures
12 lectures
Language
English

Material Includes

  • Video Lessons