Logic Synthesis is the very first step towards the physical implementation or physical design of the logic written in the form of Register transfer level(RTL). It is the process of conversion of RTL into a gate-level netlist, yes, it is the simplest definition. This conversion does not mean all to the synthesis, the most important part of the synthesis is the optimization of the netlist to make it efficient for succeeding steps. Let’s focus on the Synthesis and the steps involved in the conversion and optimization.

To make things much simpler I am taking an example of a Half-adder.

Step 1: Gate level model of Half adder.

The inputs to the synthesis process are :

1. Library for the standard cells as well as for macros.
2. RTL code.
3. Design and timing constraints.

RTL of half-adder is written in the data flow modelling. 

Step 2: Verilog code of half adder.

The code has written according to the behaviour of the logic. No hint shows how it will get implemented on the hardware or wafer. The logic synthesis tool is smart enough to make the relation of this behavioural code to the gate-level logic, so, the code will ultimately be converted into two logic gates, one is AND gate and another is XOR gate.

The tool first translates the RTL to a generic gate netlist which is technology(standard cell library) independent. The tool first converts to the generic gate-level netlist so that it can perform some important logic level optimization methods like structuring and flattening which are independent of technology.

Step 3 : GTECH netlist of half-adder.

The generic netlist is then mapped or converted into a technology-dependent netlist, generic XOR(GTECH_xr) and generic AND(GTECH_an) is replaced by the standard cells which are present in the library. This mapping step is also involved in the optimization of the netlist to meet the Design and Timing constraints.

Step 4 : Gate level netlist of half adder.

Now, we have a gate-level netlist of the half adder, this netlist will be used for the physical design and other succeeding processes.