About This Course
This is a 6-part lecture series on how to run physical verification, i.e., LVS and DRC, on a block created with a digital implementation flow (place and route). The first five parts of the lecture series is dedicated to the “digital-on-top” (a.k.a. “Fullchip”) layout-vs.-schematics (LVS) flow and the final part overviews DRC and chip finishing.
The lecture series is given by Dr. Adam Teman of the EnICS Labs Impact Center at Bar-Ilan University, based entirely on personal experience. The overview is demonstrated on a Cadence-based implementation flow (Genus+Innovus) with DRC/LVS running on Calibre tools. The designs shown in the demonstration are proprietary of BIU and no vendor or technology specific details are revealed.
The Free Courses does not include Certificate and Q&A Sections with instructor.
DISCLAIMER:
These videos are publicly available on the internet for free hence they may contain some advertisements. The ads earning goes to the respective instructor.
Curriculum
Video Lessons
Introduction to Digital-on-Top LVS8:14
Creating the LVS-ready Verilog Netlist18:24
Translating the Verilog netlist into SPICE22:10
Extracting the LVS-ready Layout netlist26:27
Running LVS comparison21:55
Fullchip DRC and Chip Finishing10:59
Your Instructors
Student Feedback
Reviews (1)
This was a very informative session on LVS and DRC. Not only was the flow explained in detail, Sir also explained in depth regarding some of the problems faced and different ways to fix it.
Explanation was clear and pace was also good.
