Static Timing Analysis is called timing sign-off methodology in the ASIC cycle because it ensures the chip is running accurately at all corners. As the sign-off cycle is complex the ST interview questions asked are also complex. I am sharing some of the commonly asked STA questions which will help fresher as well as experienced candidates.

• What is Setup and Hold time?

• • This is the most basic question asked by any interview. If you have experience unto 5 years in the field, this question is generally asked.
  • Expectation:  The interviewer expects here that you must have exact knowledge of Setup and Hold with the difference b/w them, on which edge setup and hold is checked, and why.

• Where is the setup and hold values are defined and how and where we encounter these values?

• • This question is asked to check the practical knowledge and hands-on experience on the timing.
  • Expectation: You should have knowledge about the values of setup and hold where they defined in the input(library).

• What is slack and how it is calculated to analyze the timing violations.

• • Expectation: Again, the interviewer wants to know your hands-on experience, you should explain here how you calculate the slack value for both setup and hold.

• How can we remove setup violations give methods?

• • Expectation: You should tell each method that is used to improve the setup violation, i.e. sizing of cells, the position of the cells, swapping of the cells. You should also tell that when and how we can alter uncertainty and operating frequency.

• How can we remove hold violations give methods?

• • Expectation: Same as the setup you should tell how can it improved.

• What all things you will consider if asked to write SDC file?

• • Expectation: The interviewer wants to know your understanding of the constraints and the SDC file.

• If you are given a large number of clocks in the design, How would you define the relationship between the clocks?

• • Expectation: Here, the expectation is how you handle the clock-related constraints and clock groups.

• How we define input and output delays?

• • Expectation: The interviewer wants to know how you handle the data transfers between two or more designs.

• What are timing exceptions and why we consider them while doing timing analysis?

• • Expectation: Here, the expectation is what all the timing paths and conditions we consider where timing relation must be ignored in timing analysis.

• What are virtual clocks and how we use them?

• • Expectation: You should know how we declare a virtual clock and what its use.

• How we handle and declare high fanout nets in the SDC file.

• • Expectation: How we take care of the high fanout nets like clock, resets, and enable signals.

• What are OCV and AOCV what is the difference between them?

• • Expectation: You are expected to tell the exact difference b/w them and from where derating values picked and used while doing analysis.

• What is CRPR and how we handle it in STA? Where you see its report and tool behaves on it.

• • Expectation: Here you are expected to have knowledge on the reports of the CRPR and behavior of tool and how you neglect the effect of this.

• How many corners did you use to close the design to analyze timing?

• • Expectation: Here, you should know how many corners you used, who gave you the corner list and how many iterations was used to fix the timing.

• What was the skew value of the design?

• • Expectation: The interviewer wants to ask your knowledge on the project you did, uncertainty values can also be asked along with this question.

• What is the difference b/w SPEF and DEF and where they used?

• • Expectation: Theoretical knowledge on this is sufficient but you must know what it all contains and where they are used.

• How you handle asynchronous clocks in a design.

• • Expectation: Again this question is timing-related you must have knowledge of the clock groups and the relationship between clocks.

• Can we ignore any setup or hold violation before tap-out? If yes which and why?

• • Go ahead it’s to your knowledge.

• Which violation you fix first and why (DRC/Setup/Hold)

• • Expectation: One of the important questions. Here you are expected to have knowledge about which violation you fix first and which on last. you also asked to explain why you fix them in this manner.

• How you fix max trans, max cap, and max fanout violations.

• • Give them an example of how you fix these violations.

• If you have a max trans violation but not any setup or hold violation then can you send the design to tap-out? If no then why?
  • Expectation: Here you are expected to have conceptual knowledge of this violation.