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What is FIFO?

What is FIFO? | Synchronous FIFO | Asynchronous FIFO

Synchronous FIFO A Synchronous FIFO is a First-In-First-Out queue in which there …

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Copy of Verilog Testbench

How to make Verilog Testbench

TestBench: In Verilog is a predefined sequence of input combinations to …

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Copy of Memory in Verilog

Memory in Verilog | Ram in Verilog

Memory is a collection of storage cells referenced under common name. …

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Synthesis Interview Questions - Blog Post

Synthesis Interview Questions | Synthesis FAQs

Detail synthesis flow, What are the inputs required and hand-off Detail …

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Static Timing Analysis Interview Questions - Blog Post

Static Timing Analysis (STA) Interview Questions

Static Timing Analysis is called timing sign-off methodology in the ASIC …

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Logic Equivalence Check - Blog Post

Logic Equivalence Check (LEC) Steps

Logic Equivalence Check: ASIC design cycle involves a number of stages …

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Logic Synthesis Steps

Logic Synthesis is the very first step towards the physical implementation or …

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Top 5 Books to Learn Verilog

Top 5 Books to Learn Verilog

Design through Verilog HDL If you aim to master Verilog language and become …

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